The present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted in juxtaposition over a die pad and a manufacturing technique therefor.
Each of the following documents discloses, as a semiconductor device, a structure in which a plurality of semiconductor chips are mounted in juxtaposition over a die pad.
Japanese Unexamined Patent Application Publication No. 2006-313876 (Patent Document 1) discloses a structure of a semiconductor device in which semiconductor chips of different sizes are mounted over a die pad which is disposed out of alignment with the center line of the main surface of a sealed/molded region.
On the other hand, Japanese Unexamined Patent Application Publication No. 2015-43398 (Patent Document 2) discloses a structure in which two semiconductor chips are provided over a die pad. Over one of the semiconductor chips, a single-layer interposer is further mounted such that the two semiconductor chips are electrically coupled to each other via the single-layer interposer.